Select gate self-aligned patterning in split-gate flash memory cell

ABSTRACT

An integrated circuit includes first and second gate stacks located over a dielectric layer that is in turn disposed over a semiconductor substrate. Each gate stack includes a floating gate located on the dielectric layer and a control gate located over the floating gate. A first select gate electrode is located on a side of the first gate stack and a second select gate electrode is located on a side of the second gate stack. The first and second select gate electrodes have adjacent sidewalls, each adjacent sidewall having a rounded top corner. The gate stacks may be portions of a split gate memory cell.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application claims priority to U.S. patent application Ser.No. 15/375,952 filed on Dec. 12, 2016, issued as U.S. Pat. No.9,966,380, and is a divisional application of U.S. patent applicationSer. No. 15/971,159, issued as U.S. Pat. No. 10,553,596, the entiretiesof which are incorporated herein by reference.

FIELD

Disclosed embodiments relate to split-gate flash memory cells.

BACKGROUND

Flash memory is an improved version of electrically erasable,programmable read-only memory (EEPROM) which is capable ofblock-by-block erasing. Flash memory is used in a variety ofapplications that require programmability with no loss of memory dataduring power down (non-volatility).

A particular flash memory cell is known in the art as a split-gate flashcell that comprises 2 side-by-side transistor structures that share acommon source (or drain) region that is in the middle of the flashmemory cell. In a split-gate flash cell, the select gate is formed toboth couple voltage onto the floating gate (FG) and to control a channelregion of the transistor. To accomplish these purposes, the select gateis physically formed directly overlying the substrate and overlying, ornext to, the FG. Split-gate flash cells are widely used in semiconductorindustry due to its advantage (over convention flash cells) of lowerleakage by being controlled by side gate transistors, lower programcurrent, higher endurance and improved data retention.

SUMMARY

This Summary is provided to introduce a brief selection of disclosedconcepts in a simplified form that are further described below in theDetailed Description including the drawings provided. This Summary isnot intended to limit the claimed subject matter's scope.

Disclosed embodiments recognize for split-gate flash cells that theerased bit reading current (Ir₁) depends on the select gate (or sidegate, or word line (WL)) device's channel length. In a known integrationprocess, the respective select gate electrodes are aligned to an activemoat (the active area edge) or to an edge of the control gate (CG). Dueto photolithography misalignment in these select gate formationprocesses there is a resulting critical dimension (CD) differencebetween even and odd select gates, causing an Ir₁ difference betweeneven and odd bitlines (BL) in each flash cell. Cell-to-cell select gateCD variation resulting from other process variations result in thresholdvoltage (Vt) differences, which may make the even-odd Ir₁ variation evenworse. Even-odd BL Ir₁ variation across the flash cells on a die is aproblem as it reduces the flash bitcell read margin.

Disclosed embodiments include split-gate flash memory cells (split-gateflash cells) that comprise a substrate having a semiconductor surface, afirst gate stack comprising a first CG on a first FG and a second gatestack comprising a second CG on a second FG each on a floating (ortunnel) gate dielectric layer on the semiconductor surface. A commonsource or common drain (common source/drain) is in the semiconductorsurface between the first FG and second FG. A first select gate and asecond select gate are on a select gate dielectric layer between a firstBL source/drain in the semiconductor surface and first FG and between asecond BL source/drain in the semiconductor surface and second FG,respectively. The first select gate and the second select gate each havea rounded upper corner, e.g. are spacer-shaped.

As used herein, “spacer-shaped” refers to a shape having a rectangularbottom with a rounded top corner against the FG-CG stack. In contrast,the shape of conventional select gate is rectangle in both the top andbottom corner. Disclosed split-gate flash memory cells have minimizedeven-odd BL Ir₁, and there is also a minimized even-odd BL Ir₁ acrossthe die, and across the fabricated wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will now be made to the accompanying drawings, which are notnecessarily drawn to scale, wherein:

FIG. 1 is a flow chart that shows steps in an example method forfabricating a split-gate flash cell on an integrated circuit (IC) usinga self-aligned patterning process to minimize even-odd select gate CDmisalignment, according to an example embodiment.

FIGS. 2A-2G shows successive in-process cross sectional depictionscorresponding to steps in an example method for forming of split-gateflash memory cells using a self-aligned patterning process to minimizeeven-odd select gate CD misalignment.

FIG. 3 is a block diagram depiction of a monolithic IC processor chipcombination including a non-volatile memory comprising an array ofinterconnected split-gate flash cells, according to an exampleembodiment.

DETAILED DESCRIPTION

Example embodiments are described with reference to the drawings,wherein like reference numerals are used to designate similar orequivalent elements. Illustrated ordering of acts or events should notbe considered as limiting, as some acts or events may occur in differentorder and/or concurrently with other acts or events. Furthermore, someillustrated acts or events may not be required to implement amethodology in accordance with this disclosure.

Disclosed embodiments recognize with split-gate flash cells being scaleddown in size, the select gate length becomes shorter, and thus moresusceptible to process variation, such as to gate length variationbetween the respective select gates on opposite ends of the flash cell(referred to herein as even/odd select gates, and their lengthdifference an even/odd select gate CD variation) that influence theselect gate Vt. Broadening of the select gate Vt distribution within thedie and die-to-die across the substrate (e.g., wafer) undesirablytranslates into a larger reading current (Ir) distribution within thedie and die-to-die across the wafer, as well as reduced flash circuitdesign margins.

A known solution used in split-gate flash cell integration to reduceeven/odd select gate CD variation is to tighten the select gatephoto-alignment margin, such as by employing improved lithographyapparatus. However, it is recognized that known tightening of the selectgate photo alignment margin is limited in effectiveness because thealignment margin cannot be made to be zero so that an even/odd selectgate CD difference generally always exists.

FIG. 1 is a flow chart that shows steps in an example method 100 forfabricating a split-gate flash memory cell that utilizes a self-alignedselect gate spacer etch patterning process to minimize even-odd selectgate CD misalignment, and thus reduces the Ir₁ difference between evenand odd BLs, according to an example embodiment. The split-gate flashcell can be based on either n-channel metal-oxide semiconductor (NMOS)or p-channel MOS (PMOS) transistors. Although NMOS transistors maygenerally be described herein, it should be clear to one having ordinaryskill in the art to use this information for PMOS transistors as well,by n-doped regions being substituted by p-doping and vice versa.Disclosed embodiments can be applied to NOR or NAND-based flash memorydesigns.

Step 101 comprises providing an in-process IC comprising a substratehaving a semiconductor surface including a first gate stack including afirst CG on a first FG and a second gate stack including a second CG ona second FG, each on a floating gate dielectric layer on a semiconductorsurface of a substrate. A common source/drain is in the semiconductorsurface between the first FG and second FG, and at least one dielectriclayer is on sidewalls of the first gate stack and on sidewalls of thesecond gate stack.

Step 102 comprises depositing a first gate electrode layer includingover the first gate stack and over the second gate stack. A typicalthickness range for the first gate electrode layer is 80 nm to 160 nm.FIG. 2A is a cross sectional depiction of the resulting in-process ICincluding a split-gate flash cell following the first gate electrodelayer deposition (step 102) described as being a polysilicon depositionthat forms a polysilicon layer 260 over the gate stacks for what will bedefined by later steps in method 100 into select gates. The first gatestack comprises the first CG 230 on the first FG 210 and a second gatestack comprises the second CG 240 on the second FG 220. The first gateelectrode layer may also comprise a metal material (e.g., metal or metalalloy) to realize metal gates. For example, Low-Pressure Chemical VaporDeposition (LPCVD) can be used to deposit the first gate electrodelayer. There are dielectric layers on the sidewalls of the gate stacksshown in FIG. 2A including a first dielectric layer 237 (e.g., siliconoxide) on a second dielectric layer 238 (e.g., silicon nitride) on athird dielectric layer 239 (e.g., silicon oxide) that collectivelyprovide electrical isolation for the CG and FG of the gate stacks.

The in-process IC comprises a substrate 205 having a semiconductorsurface 205 a. The substrate is generally in wafer form having aplurality of die. The substrate 205 can comprise silicon,silicon-germanium, or other semiconductor materials including III-V orII-VI materials, and can comprise a bulk substrate or an epitaxial layeron a bulk substrate. One particular arrangement is a silicon/germanium(SiGe) semiconductor surface on a silicon substrate.

The first FG 210 and second FG 220 are on a floating gate dielectriclayer 211 on the semiconductor surface 205 a. There is a dielectricstack between the CGs and FGs comprising a first dielectric layer 234,second dielectric layer 235 and a third dielectric layer 236. A commonsource/drain 245 shown as a common source (CS) is in the semiconductorsurface 205 a between the first FG 210 and second FG 220 shown having adielectric layer 231 thereon. Shown on CG 230 and 240 is a siliconnitride layer 242.

On the same IC die is shown a logic region 270 where logic gates areformed and a region 280 where “strap cells” are formed. Dielectricisolation is shown as shallow trench isolation (STI) 255. The logicregion 270 showing a logic well where logic gates are formed and the“strap cell” in region 280 are provided to show disclosed processing isfor generally forming flash memory devices embedded with logic devicesand disclosed processing will not add any new masks, even for flashmemory having strap cells. However, disclosed embodiments may also beused for stand-alone split-gate flash cell memory. A flash “strap cell”is used for connections through metal(s) to couple to the CGs 230, 240,CS 245 or select gate transistors, which are generally within a 2D flasharray.

The floating gate dielectric layer 211, such as a dielectric oxide(e.g., silicon oxide) layer, may be for example between about 5 nm and12 nm in thickness. The floating gate dielectric layer 211 is selectedto be relatively thin to allow charge transfer to the FGs 210, 220 aboveduring programming or erasing, but thick enough to provide good chargeretention during non-programming and non-erasing operation. Because theFGs 210, 220 are electrically isolated by their floating gate dielectriclayer 211 from the semiconductor surface 205 a, electrons reaching itare trapped until they are removed by another application of electricfield (e.g., an applied voltage or ultraviolet (UV) light as in erasableprogrammable read-only memory (EPROM)).

Step 103 comprises forming a patterned capping dielectric layerincluding over a logic region 270 on the IC that includes logic gates.The patterned capping dielectric layer is for keeping the logic CMOSgate electrode layer thickness controlled only by the first gateelectrode layer deposition, so it is not changed by the second gateelectrode layer deposition (step 104 described below) or theanisotropically etching step (step 105 described below). FIG. 2B is across sectional depiction of the resulting in-process IC including asplit-gate flash cell following step 103 that adds a patterned cappingdielectric layer 285. The patterning generally comprises using aphotoresist pattern. The patterned capping dielectric layer 285 coversthe flash periphery logic in the logic region 270 and the strap cells inthe flash array in region 280.

Step 104 comprises depositing a second gate electrode layer includingover the first gate stack, over the second gate stack, and over thepatterned dielectric layer. For example, LPCVD can be used to deposit 10nm to about 100 nm of the second gate electrode layer material. Thesecond gate electrode layer can comprise polysilicon or a metalmaterial. FIG. 2C is a cross sectional depiction of the resultingin-process IC including a split-gate flash cell following a second gateelectrode layer shown as a second polysilicon 290 which is used toadjust the polysilicon film thickness in the flash array to target thefinal select gate CD that is provided after step 105 (anisotropic gateelectrode layer etch) described below.

It is recognized that as the deposited second polysilicon 290 filmthickness (or other second gate electrode layer) increases, the width ofthe thick polysilicon region (or other second gate electrode layer)along the sidewalls of the gate stacks increases. As noted above thethickness range for this second polysilicon deposition generally variesfrom 10 nm to 100 nm, where a thicker second polysilicon depositionleads to larger select gate CD and a thinner deposition leads to asmaller select gate CD.

Step 105 comprises anisotropically etching including etching both thefirst and second gate electrode layers to form spacer-shaped select gatespacers along the sidewalls of the first gate stack to provide a firstselect gate on a select gate dielectric layer on the semiconductorsurface and a spaced apart second select gate on the select gatedielectric layer. The select gate dielectric layer 216 can comprise ahigh-k dielectric layer being defined as a material with a dielectricconstant κ of at least 5 compared to that of silicon dioxide being about3.9. FIG. 2D is a cross sectional depiction of the resulting in-processIC including a split-gate flash cell following step 105 showing an evenselect gate 215 and an odd select gate 225 both on a select gatedielectric layer 216. The even select gate 215 and odd select gate 225can both be seen to be spacer-shaped.

The select gate CD is defined by this spacer-like etch, such as aspacer-like polysilicon etch, where no masking layer is needed. Aspacer-like etch as used herein is an anisotropic plasma etch, such asin one specific embodiment to anisotropically etch polysilicon using amixed etch gas comprising HBr and Cl₂ under conditions of chamberpressure of about 3 mT to 30 mT and RF bias power of about 40 W to 100W. Generally using a high power and low pressure increases the energyand strength of the ion bombardment of the wafer, leading to directionaletching (anisotropic) with more anisotropy.

This anisotropic plasma etch can be for removing all the secondpolysilicon 290 film on the flat surfaces of the die which had arelatively lower film polysilicon thickness, while keeping a portion ofthe polysilicon film from polysilicon layer 260 along the sidewalls ofthe gate stacks that as noted above had a relatively high film thicknessas deposited. Thus, the spacer CD following the spacer-like etch (step105) depends on the deposited second polysilicon 290 film thickness.Although not shown, there can be a silicide layer on the select gates215 and 225 shown in FIG. 2D which will generally be the case when thesegates comprise polysilicon.

Step 106 comprises removing the patterned capping dielectric layer. FIG.2E is a cross sectional depiction of the resulting in-process ICincluding a split-gate flash cell following step 106 reflecting theremoval of the capping dielectric layer 285.

Step 107 comprises patterning logic gates and flash strap cell gates.FIG. 2F is a cross sectional depiction of the resulting in-process ICincluding a split-gate flash cell following step 107 showing a patternedlogic gate 271 and patterned strap cell 281.

Step 108 comprises forming a first BL source/drain in the semiconductorsurface 205 a adjacent to the first select gate and a second BLsource/drain in the semiconductor surface adjacent to the second selectgate. FIG. 2G is a cross sectional depiction of an example in-process ICincluding a split-gate flash cell shown as 295 following step 108 thatforms the BLs 218 and 228. The BLs are generally formed by ionimplantation with a mask. LDDs region 219 and 229 are also shown thatcan be formed by an ion implant with a mask. Optionally, although notshown, a pocket implant can also be included. Contacts and themetallization stack over the split-gate flash cell 295 are not shown inFIG. 2G for simplicity. The polysilicon spacer between the gate stacksnow labeled as 248 is shown extending on top of the CS 245 and can serveas a dummy gate resulting from the self-aligned gate electrode etch oras an erase gate (EG).

Disclosed select-gate patterning processes in split-gate flash cell haveunique features(s). Such features include anisotropic polysilicon (orother second gate electrode layer) spacer etch that forms spacer-shapedselect gates, self-alignment of the select-gates to the FG-CG stacks,the select-gate CD being adjustable to the technology target by tuningthe polysilicon (or other second gate electrode layer) thickness, and noneed for any adding mask compared with a conventional non-self-alignedselect-gate patterning process. The CD difference between the firstselect-gate and the second select-gate provided is at a minimum with noconventional CD difference contribution from photo-misalignment.

Advantages of disclosed methods enabled by self-aligned select gatepatterning methods include essentially eliminating the even-odd selectgate CD misalignment, thus reducing the even-odd Ir₁ variation acrossthe die, die-to-die, and across the wafer. Disclosed methods also do notutilize a conventional spacer hard mask for select gate electrodepatterning. Disclosed methods thus do not require sacrificial layerphoto patterning, and as a result there is no extra photo mask needed.

FIG. 3 is a block diagram depiction of a monolithic IC processor chipcombination (IC combination) 300 formed in and on a semiconductorsurface 205 a of a substrate 205 including a non-volatile memory 372comprising an array of interconnected disclosed split-gate flash cells295, according to an example embodiment. The connection between thesplit-gate flash cells 295 can be in parallel to the bit lines so thateach cell can be read/written/erased individually, or connected inseries. On-chip flash memory is perhaps the most important memoryelement in any application since it is most often the source for all theinstructions for the central processing unit (CPU) 375. If instructionsare not fetched efficiently, the overall processor performance willlikely suffer. The IC combination 300 can comprise a microprocessor,digital signal processor (DSP) or microcontroller unit (MCU).

Although not shown, the IC combination 300 generally includes otherintegrated circuit modules, for example, a Universal Serial Bus (USB)controller and a transceiver. IC combination 300 is shown includingADC's 343 a, 343 b, PWM driver 355, volatile data memory 373, digitalI/O (interface) 374, and clock (or timer) 376. IC combination 300 isalso shown including a digital data bus 378 and an address bus 379.

Disclosed embodiments can be used to form semiconductor die that may beintegrated into a variety of assembly flows to form a variety ofdifferent devices and related products including embedded technology ofsplit-gate flash cells integrated with CMOS logic, and also stand-alonesplit-gate flash cell memory. The semiconductor die may include variouselements therein and/or layers thereon, including barrier layers,dielectric layers, device structures, active elements and passiveelements including source regions, drain regions, bit lines, bases,emitters, collectors, conductive lines, conductive vias, etc. Moreover,the semiconductor die can be formed from a variety of processesincluding bipolar, Insulated Gate Bipolar Transistor (IGBT), CMOS,BiCMOS and MEMS.

Those skilled in the art to which this disclosure relates willappreciate that many other embodiments and variations of embodiments arepossible within the scope of the claimed invention, and furtheradditions, deletions, substitutions and modifications may be made to thedescribed embodiments without departing from the scope of thisdisclosure.

What is claimed is:
 1. A split-gate memory cell, comprising: a semiconductor substrate; a dielectric layer disposed over the semiconductor substrate; a first gate stack disposed over the dielectric layer and including a first control gate arranged over a first floating gate; a second gate stack disposed on the dielectric layer and including a second control gate arranged over a second floating gate; a common source/drain disposed in the semiconductor substrate and extending from the first floating gate to the second floating gate; a first spacer-shaped select gate disposed on the dielectric layer and arranged between the first floating gate and a first bitline source/drain disposed in the semiconductor substrate; and a second spacer-shaped select gate disposed on the dielectric layer and arranged between the second floating gate and a second bitline source/drain disposed in the semiconductor substrate.
 2. The split-gate memory cell of claim 1, wherein each of the first bitline source/drain and the second bitline source/drain connects the split-gate memory cell to a bitline of a memory array in which the split-gate memory cell is arranged.
 3. The split-gate memory cell of claim 1, wherein the first spacer-shaped select gate, the second spacer-shaped select gate, the first control gate, and the second control gate are polysilicon gate structures.
 4. The split-gate memory cell of claim 1, wherein the first spacer-shaped select gate, the second spacer-shaped select gate, the first control gate, and the second control gate are metal gate structures.
 5. An integrated circuit, comprising: first and second gate stacks located over a dielectric layer that is disposed over a semiconductor substrate, each gate stack including a floating gate located on the dielectric layer and a control gate located over the floating gate; a first select gate electrode located on a side of the first gate stack and a second select gate electrode located on a side of the second gate stack, the first and second select gate electrodes having adjacent sidewalls, each adjacent sidewall having a rounded top corner.
 6. The integrated circuit of claim 5, further comprising a common source/drain disposed in the semiconductor substrate and extending from the first floating gate to the second floating gate.
 7. The integrated circuit of claim 5, further comprising a tri-layer dielectric stack between the floating gate and the control gate of the first gate stack, and between the control gate of the first gate stack and the first select gate electrode.
 8. The integrated circuit of claim 5, further comprising a third select gate electrode on a side of the first gate stack opposite the first select gate electrode, and a fourth select gate electrode on a side of the second gate stack opposite the second select gate electrode.
 9. The integrated circuit of claim 8, further comprising first bitline source/drain region extending under the third select gate electrode and a second bitline source/drain region extending under the fourth select gate electrode.
 10. An integrated circuit, comprising: first and second gate electrodes located over a dielectric layer, the first gate electrode having a first side with a rounded corner, and the second gate electrode having a second side with a rounded corner, the first side facing away from the second side; a third gate electrode between the first and second gate electrodes; and a fourth gate electrode between the third gate electrode and the dielectric layer.
 11. The integrated circuit of claim 10, further comprising: fifth and sixth gate electrodes located over the dielectric layer, the fifth gate electrode having a third side with a rounded corner, and the sixth gate electrode having a fourth side with a rounded corner, the third side facing away from the fourth side; a seventh gate electrode between the fifth and sixth gate electrodes; and an eighth gate electrode between the seventh gate electrode and the dielectric layer.
 12. The integrated circuit of claim 11, further comprising a first implanted region under the second and fifth gate electrodes.
 13. The integrated circuit of claim 12, further comprising a common source/drain region between and under the second and fifth gate electrodes, a first bit-line source/drain region located adjacent the first gate electrode, and a second bit-line source/drain region located adjacent the sixth gate electrode, and a second bit-line source/drain region located adjacent the sixth gate electrode.
 14. The integrated circuit of claim 12, further comprising a second implanted region adjacent the first gate electrode, the first gate electrode being between the first implanted region and the fourth electrode.
 15. The integrated circuit of claim 14, further comprising an extension of the second implanted region under the first gate electrode.
 16. The integrated circuit of claim 11, wherein the third and fourth gate electrodes are part of a first gate stack of a split-gate memory cell, the and seventh and eighth gate electrodes are part of a second gate stack of the split-gate memory cell.
 17. The integrated circuit of claim 16, wherein the split gate memory cell is configured to store data under control of a central processing unit.
 18. The integrated circuit of claim 16, wherein the split gate memory cell is one of a plurality of split gate memory cells arranged in a memory array.
 19. The integrated circuit of claim 10, wherein the first, second, third and fourth gate electrodes are formed from polysilicon.
 20. The integrated circuit of claim 10, further comprising a tri-layer dielectric stack between the first gate electrode and the third and fourth gate electrodes. 